Fault Tolerance Techniques For Highly Parallel Signal Processing Architectures
Jacob A. Abraham · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1986
This overview paper describes techniques for fault tolerance which can be applied to highly parallel signal processing architec-tures. Classical techniques are outlined and shown applicable to memories and data communications. The recent approach of algorithm-based fault tolerance, which tailors the fault tolerance to the systolic algorithm and processor architecture, is shown to be a natural one for such systems. Various data encoding techniques and resulting fault-tolerant systems are described and critiqued.