ASIC design of 7.7 Gbps multi-mode LDPC decoder for IEEE 802.11ac
Thi Hong Tran, Yuhei Nagao, Hiroshi Ochi, Masayuki Kurosaki · 2014
In this paper, we propose a multi-mode low density parity check (LDPC) decoder architecture for high throughput wireless communication systems. Throughput of our decoder depends on code rate. The main blocks of our architecture are independent from value of the check matrix. Based on the proposed architecture, we design a twelve-mode Min-Sum LDPC decoder for IEEE 802.11ac system and synthesize it in ASIC 90nm technology. The ASIC synthesis results show that our decoder achieves up to 15.4 bits/cycle (bpc) or 7.7 Gbps at 500 MHz operating frequency, and has the best efficiency which is 1.89 (bpc/mm2) as compared to the previous works. In this paper, we also propose an efficient quantization method that can significantly improve the PER performance. The floating point and fixed point simulation results show that PER performance of the 802.11ac system is improved by at least 1 dB if using LDPC instead of BCC. Furthermore, the proposed quantization method can improve the LDPC PER performance up to 1.7 dB.