Effects of address interleaving on multiprocessor instruction - accessing memory interference
Peter T. Rux · Annual Simulation Symposium · 1973
In the classical multiprocessor configuration with a set of processors accessing a common set of memory modules, there is a loss in processor efficiency due to interference among the processors when accessing instructions or data. GPSS (General Purpose Simulation System) simulation experiments have been run to evaluate the effects of various address interleaving strategies on instruction-accessing interference. The important parameters in these experiments are the number of processors and memory modules, the degree of address interleaving, and the average consecutive instruction sequence length. The results support the following conclusions: (1) Address interleaving can substantially reduce instruction-accessing memory interference. (2) The amount of improvement increases with either a higher interleaving factor or a longer average consecutive instruction sequence length. (3) For minimum interference, the interleaving factor need not be larger than the average consecutive instruction sequence length.