Functional verification of power gate design in SystemC RTL
George Sobral Silveira, Alisson V. Brito, Elmar U. K. Melcher · 2009
With the growth of number of transistors, thermal density and market drive towards battery power, the necessity to develop low power integrated circuits is evident. There are several methodologies and techniques that help in the development of this type of SoC. There is consensus that the techniques when applied in the initial phases of the design flow, especially in design and architecture of the system have a higher impact factor in relation to those applied during the implementation or layout phase. Considering this fact, the possibility to accomplish functional verification of the system with low power design modeled in TLM and RTL is attractive. The purpose of this paper is to show a method for functional verification of power gate design in RTL. A case study is presented to demonstrate the application of power gate using new features for the OSCI SystemC simulator developed for this purpose and the accomplishment of the functional verification of the design using the VeriSC methodology.