VLSI configurable delay commutator for a pipeline split radix FFT architecture
Jesús L. Llano García, Juan A. Michell, Angel M. Buron · IEEE Transactions on Signal Processing · 1999
This paper presents a full custom one-bit slice delay commutator for a pipeline split radix FFT (SRFFT) architecture, implemented using the true single-phase-clock (TSPC) circuit technique and a 1.0-/spl mu/m CMOS technology. This circuit can be configured or all intermediate SRFFT computation levels for transforms of lengths up to N=2048, where N is power of two. The circuit has been tested up to 200 MHz, having a power consumption of 1.1 W at 5 V of power supply.