A fast virtual device framework for improving RTL verification efficiency
Jianfeng An, Xiaoya Fan, Shangang Zhang · 2011
Functional verification is time-consuming in design of processors. In order to rapidly build a reference model and automatically compare simulation resulting, this paper proposes a virtual device framework based full system simulator. The framework can speed up construction of verification environment for processors, from internal components to full processors. We demonstrate the method using the decoder component verification in Longteng C1 processor. The result shows the framework is efficient.