A nonsorting VLSI structure for implementing the (M, L) algorithm
S.J. Simmons · IEEE Journal on Selected Areas in Communications · 1988
A nonsorting structure for implementing the (M, L) algorithm is presented. The processing is based on a survivor selection operation that incorporates parallelism and has an execution time proportional to the product of the logarithm of bM (the number of contender paths), and k (the number of bits used for path metrics). Aside from the path extender(s), the processor area is only a small fraction of the total chip area; most is simply for required storage of path histories and metrics. This means that the structure can support a large M on a single chip. In addition, the structure can be extended to larger M by stacking rows of a few different types of custom chips.>