A victim cache for vector registers
Roger Espasa, Mateo Valero · 1997
In this paper we introduce the concept of a victim cache for the register level of a vector processor. This small cache holds full vectors "evicted" from the register level through store instructions. The goal of this cache is to filter out the abundant spill code present in vector programs. Using a trace driven simulation technique we compare the performance of a conventional vector implementation with and without the addition of the victim cache proposed. We study a writethrough victim cache that eliminates around a 5--20% of load spill traffic and provides speedups in the range 1.06--1.20. In order to allow elimination of store spill traffic, we also present a write-back victim cache that increases the amount of traffic eliminated up to the 10--50% range. Finally, we study the behavior of the victim cache under different memory latencies and show that the victim allows a good tolerance of large memory latencies and can provide speedups as large as 1.24. 1 Introduction Spill code i...