Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification
Yong-Ha Park, Seon‐Ho Han, Hoi‐Jun Yoo · 2001
A single chip rendering engine that consist of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32b RISC core is proposed for the low power 3D-graphics in portable system. The 56mm2 prototype integrating edge processor, 8 pixel processors, 8 frame buffers and RISC core is fabricated using 0.35um CMOS Embedded Memory Logic (EML) technology.