A Practical Real Time Svd Machine With Multi-Level Fault Tolerance
David E. Schimmel, Franklin T. Luk · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1986
A fault tolerant systolic processor system is proposed for computing the singular value decomposition of an nxn matrix. This approach uses only orthogonal interconnections and simple multiply and accumulate processors in the array. The fault tolerant properties are achieved through a composite of simple low overhead structures. The square root computations, and all fault tolerance computations are performed in one highly pipelined boundary processor. The architecture requires 0(n) processors and 0(n2 log n) time.