BIT-LEVEL SYSTOLIC ARRAYS FOR DIGITAL CONTOUR SMOOTHING BY ABEL-POISSON KERNEL
Ján Glasa · Parallel Processing Letters · 1993
Two different bit-level systolic arrays for digital contour smoothing by Abel-Poisson kernel which minimize the execution time and the number of functional elements required are suggested. The arrays are fully pipelined on the bit-level achieving very high clock frequency. They are implementable in VLSI and are dedicated for real-time applications.