Formal Verifications in Modern Chip Designs
Kei-Yong Khoo · Proceedings · 2006
Summary form only given. Formal technologies have matured rapidly in recently years to become an indispensable technology powering many practical and production-proven formal verification solutions. In this presentation, we survey how formal technologies have enabled logic equivalence checking, design-constraint management, and low-power design verifications. In addition, we examine modern and emerging design styles and techniques, and requirements on formal technologies to meet the new verification challenges