Verifying SystemC using an intermediate verification language and symbolic simulation
Hoang M. Le, Daniel J. Grosse, Vladimir Herdt, Rolf Drechsler · 2013
Formal verification of SystemC is challenging. Before dealing with symbolic inputs and the concurrency semantics, a front-end is required to translate the design to a formal model. The lack of such front-ends has hampered the development of efficient back-ends so far.