APEnet+ 34 Gbps data transmission system and custom transmission logic
Roberto Ammendola, A. Biagioni, Ottorino Frezza, A. Lonardo, Francesca Lo Cicero, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, P. Vicini · Journal of Instrumentation · 2013
APEnet+ is a point-to-point, low-latency, 3D-torus network controller integrated in a PCIe Gen2 board based on the Altera Stratix IV FPGA. We characterize the transmission system (embedded transceivers driving external QSFP+ modules) analyzing signal integrity, throughput, latency, BER and jitter at different data rates up to 34 Gbps. We estimate the efficiency of a custom logic able to sustain 2.6 GB/s per link with an FPGA on-chip memory footprint of 40 KB, providing deadlock-free routing and systemic awareness of faults. Finally, we show the preliminary results obtained with the embedded transceivers of a next-generation FPGA and outline some ideas to increase the performance with the same FPGA memory footprint.