Process evaluation test structures and measurement techniques for a planar GaAs digital IC technology
Ricardo R. L. Zucca, Bryant M. Welch, Chien-Ping Lee, Richard C. Eden, S.I. Long · IEEE Transactions on Electron Devices · 1980
The successful development of a new integrated circuit (IC) technology requires a significant effort in process evaluation. This is particularly true for the high-speed low-power planar GaAs digital IC technology, which involves a relatively new semiconductor material, new processing techniques, and pursues LSI complexity using very-fine-line lithography (1-µm dimensions). This paper contains a review of the strategy employed to monitor and evaluate each of the key process steps, and to evaluate the uniformity of device parameters. The principal process evaluation test structures are discussed along with measurement techniques, and examples of measurement results are given. Our emphasis on measurement automation to facilitate the collection of a large volume of data and their statistical analysis is reflected in the paper. Examples of wafer statistics are given.