Dynamic switching of coherent cache protocols and its effects on Doacross loops
Takashi Matsumoto, Kei Hiraki · 1993
In multiprocessor systems, overheads caused by interprocessor communication and synchronization have been one of the largest obstacles for efficient execution of parallel programs. To reduce these overheads in shared-memory/shared-bus multiprocessors, we have proposed two hardware mechanisms: the Inter-Cache Snoop Control Mechanism (ICSCM), which dynamically switches snoop-protocols for improving shared-bus utilization, and the Mechanism for Integrated Synchronization and Communication (MISC), which extends ICSCM to support producer-consumer type synchronization efficiently. We have developed an execution-driven multiprocessor simulator for evaluating performance with these mechanisms. Simulation experiments on doacross loops show remarkable speed-ups by ICSCM/MISC mechanisms. Although the proposed mechanisms are originally implemented on a single shared-bus system, they are easily applicable to a clustered multiprocessing systems. The methods used in a clustered system are discussed.