A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling
Kieran McLaughlin, Siren Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Thomas Noll · 2006
A novel implementation of a tag sorting circuit for a weighted fair queuing (WFQ) enabled IP packet scheduler is presented. The design consists of a search tree, matching circuitry and a custom memory layout. The implementation uses 130 nm silicon technology and supports quality of service on networks at line speeds of 40 Gbps.