Demonstration of an 8×8-bit RSFQ multi-port register file
Alex F. Kirichenko, Anubhav Sahu, Timur V. Filippov, Oleg A. Mukhanov, Andriy V. Dotsenko, M. Dorojevets, Artur K. Kasperek · 2013
As a part of the 8-bit RSFQ processor datapath development, we have designed, fabricated, and experimentally demonstrated an 8×8-bit RSFQ multi-port register file. The register file provides input data operands and stores Arithmetic Logic Unit (ALU) results. It can perform two simultaneous non-destructive “read” operations and one “write” operation and is capable of storing eight 8-bit words. The distinct feature of the design is an extensive use of passive transmission lines (PTLs) for very complex interconnects inside the register file. The register file is designed for integration with recently demonstrated 20-GHz 8-bit RSFQ ALU. It is fabricated with the standard HYPRES's 1.0-um 4.5-kA/cm2process. The circuit is placed on a 1 cm × 1 cm chip and consists of ~4,000 Josephson junctions.