Frequency-dependent performance analysis of a parallel DSP-based computer system
Ch. S. Christou · AIP conference proceedings · 2014
The performance of a shared-memory low-cost high-performance DSP-Based multiprocessor system [3] is investigated, by varying the frequency of the core processor from 200MHz to 1GHZ, in steps of 200 MHZ, and keeping constant parameters such as the shared-memory-access-time and the prefetching-workload-size. The innovation of this Parallel DSP-Based computer system is the introduction of two small programmable small fast memories (Twins) between the processor and the shared bus interconnect. While one memory (Twin) transfers data from/to the shared memory, the other Twin supplies the core DSP-processor with data. Results indicate an increase of the shared-bus bottleneck as the core DSP processors' clock-rate increases. Workload of the Twins is processed faster thus greater the demand of the shared-bus. Results show an effectively supported robust parallel shared-memory system where fewer but faster (clocked with higher frequency) processors produce the same execution times as a greater number of slower processors, with most system configurations achieving perfect speedups, mainly due to the twin-prefetching mechanism.