Characterization of a low-power 6.4 Gbps DDR DIMM memory interface system
Ravi T. Kollipara, Sam Y. Chang, Chris Madden, Hai Lan, Liji Gopalakrishnan, Scott Best, Yi Lu, Sanath Bangalore, Ganapathy E. Kumar, Pravin Kumar Venkatesan, Kapil Vyas, Kashinath Prabhu, Kambiz Kaviani, Michael Bucher, Lei Luo · 2013
A memory system that meets the bandwidth, power efficiency, and capacity needs of future computing systems is presented in this paper. A 6.4 Gbps single-ended DDR memory interface for the controller and the DRAM was designed in a 28-nm CMOS process for a main memory system with dual-rank DIMMs. The architecture features a novel clocking scheme, per-pin timing adjustment, dynamic point-to-point signaling topology, and near ground signaling. The system V-T budget simulations and the characterization results of the fabricated memory interface are presented.