Optimal power reduction based on DVFS algorithm for video decoders
Seungho Jeong, Heejune Ahn · 2011
This paper proposes an optimal DVFS (Dynamic Voltage and Frequency Scaling) scheduling algorithm for decoders. Many DVFS techniques for video decoders have been proposed as a system level power-reduction technique. In this paper, based on the similarity in the system model with the 'Maximal Traffic Smoothing Algorithm [1],' an optimal scheduling algorithm and its schedulable conditions are presented. The simulation results show the optimal algorithm outperforms the previous heuristic algorithms by 7% on average. Furthermore, the performance gain saturates at about 10 frame size of the display buffers, i.e. the GOP level.