A Hardware Scheduler for Real Time Multiprocessor System on Chip
Nikhil Gupta, Suman K. Mandal, Javier Malave, Ayan Mandal, Rabi Mahapatra · 2010
This paper presents the design and implementation of a low-power hardware scheduler for multiprocessor system-on-chips. The Pfair scheduling algorithm is considered with three different implementation schemes: replicated software scheduler running on each processor, single software scheduler running on a dedicated processor and the proposed hardware scheduler. Experimental evaluation with benchmarks shows that the hardware scheduler outperforms the other two schemes in terms of energy consumption by an order of magnitude of 105and scheduling delay by an order of magnitude of 103.