Improvements on the detection of false paths by using unateness and satisfiability
Felipe de Souza Marques, Osvaldo Martinello, Renato P. Ribas, Andre Inacio Reis · 2010
This paper presents improvements on a previous methodology for false path detection using satisfiability. As the previous methodology, which is referred as node-sat, it is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sets of clauses associated to paths, the node-sat can be more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths, and therefore, a smaller number of satisfiability instances needs to be solved. This number can be reduced even more by considering the circuit topology. Experiments comparing the previous node-sat methodology and the new techniques presented on this paper reveal that the execution time is reduced by 60% on average.