A new architecture for hardware implementation of a 16 × 16 discrete cosine transform
Chau‐Yun Hsu, Herb-Dee Wu · International Journal of Electronics · 1992
The two-dimensional discrete cosine transform (2D DCT) has been widely applied in image and video signal compression. A direct hardware implementation of the 16×16 DCT requires many multipliers. As the circuit of a multiplier is very complex, we propose an efficient hardware realization of the 16 × 16 DCT. The new structure requires no multipliers. A concurrent architecture for a 16 × 16 DCT using the permuted difference coefficient (PDC) algorithm is presented. The advantages of this new architecture are high speed, high accuracy, and efficient hardware realization. This proposed architecture has been demonstrated for a 16 × 16 DCT with the simulation of finite word-length. The simulation results shows that our development is quite attractive for digital image compression.