A new pipelined decoder of error‐correction codes for a sync‐out data sequence of digital VTRs
Junko Nakase, Nobukazu Doi, Toshiji Nakatomi · Electronics and Communications in Japan (Part II Electronics) · 1995
Abstract The error‐correcting decoder is designed assuming that the input data have a constant data length. In the case of digital video technology recorders (VTR), however, there is a possibility that the length of the playback data sequence changes by desynchronization. This paper proposes an independent reset‐type error‐correcting decoder that can cope with the playback data sequence with varying data length. In the independent reset method, the signal indicating the end of processing in the operational block composing the pipeline is used as the reset signal for the operational block in the next stage. By this mechanism, a sufficient time for the operation is secured for each operational block, even if the data length of the input data varies. By applying the proposed method to the D2 digital VTR system, the miscorrection probability is examined. It is then shown that the miscorrection probability can be decreased compared to the conventional method, both in the normal and the special playback. Using the proposed independent reset method, the error‐correcting LSI decoder based on the Reed‐Solomon code is constructed. LSI is shared by the decoding processes of the inner and the outer codes of D2 system. LSI is designed so that up to 4 Bytes can be corrected for both random error and erasure corrections. The additional circuit complexity due to the independent reset mechanism is several percent of the whole LSI.