Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits
Nobuaki Kobayashi · IEICE Transactions on Electronics · 2006
To drastically reduce the dynamic power (P AT ) and the leakage power (P ST ) of the CMOS MPEG4/H.264 motion estimation (ME) circuits, several power reduction techniques were developed. They were circuit architectures, which were able to reduce the supply voltages (V DD ) and numbers of logic gates of not only the whole circuit but the critical path, a fast motion estimation algorithm, and a leakage current reduction circuit. A 0.18-μm CMOS ME circuit has been fabricated by adopting those techniques. At a clock frequency of 160 MHz and V DD of 1.25 V, P AT decreased to 75.9μW, which was 5.35% that of a conventional ME circuit. P ST also decreased to 0.82 nW, which was 3.93% that of the conventional ME circuit.