Performance analysis of input and output queuing ATM switch with two speedup factors
Masaki Bandai, Masaki Umayabashi, Shigeki Shiokawa, Iwao Sasase · Electronics and Communications in Japan (Part I Communications) · 1999
Recently, to handle large amounts of information more rapidly and reliably, the role of ATM switches in networks has become important. The conventional input and output queuing ATM switch model with a large speedup factor can achieve superior delay reduction performance. However, because of overflow in the output buffer, the cell loss probability is large. In this paper, to decrease cell loss probability, an input and output queuing ATM switch model with two speedup factors is proposed. In the proposed model, a large speedup factor is basically used, although a small speedup factor is adopted when the output queue length exceeds a threshold in the previous time slot. We evaluate the mean waiting time and cell loss probability by theoretical analysis and computer simulations. We show that the proposed model is useful in decreasing the cell loss probability without increasing the mean waiting time excessively. © 1999 Scripta Technica, Electron Comm Jpn Pt 1, 82(10): 20–28, 1999