A systolic array architecture for multiplying Toeplitz matrices
S. Sureshchandran · 1992
Article Free Access Share on A systolic array architecture for multiplying Toeplitz matrices Author: S. Sureshchandran Department of Computer and Information Sciences, University of Delaware Department of Computer and Information Sciences, University of DelawareView Profile Authors Info & Claims SAC '92: Proceedings of the 1992 ACM/SIGAPP symposium on Applied computing: technological challenges of the 1990'sMarch 1992 Pages 933–936https://doi.org/10.1145/130069.130110Published:01 March 1992Publication History 0citation274DownloadsMetricsTotal Citations0Total Downloads274Last 12 Months7Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF