Optimal matrix multiplication on fault-tolerant VLSI arrays
Peter Varman, I. V. Ramakrishnan · IEEE Transactions on Computers · 1989
A fault-tolerant array for matrix multiplication that explicitly incorporates mechanisms for easy testability and reconfigurability is described. All signals in the array travel only a constant distance (independent of array size) in any clock cycle. An optimal-time algorithm, designed for multiplying matrices, is described. The algorithm is an efficient simulation of a 2-D systolic algorithm for multiplying matrices.>