Coping with latency in SOC design
Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli · IEEE Micro · 2002
Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency's increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process.