Unified architecture for 2, 3, 4, 5, and 7‐point DFTs based on Winograd Fourier transform algorithm
Fahad Qureshi, Mario Garrido, Oscar Gustafsson · Electronics Letters · 2013
A unified hardware architecture that can be reconfigured to calculate 2, 3, 4, 5, or 7‐point DFTs is presented. The architecture is based on the Winograd Fourier transform algorithm and the complexity is equal to a 7‐point DFT in terms of adders/subtractors and multipliers plus only seven multiplexers introduced to enable reconfigurability. The processing element finds potential use in memory‐based FFTs, where non‐power‐of‐two sizes are required such as in DMB‐T.