Universal built-in self-test procedure for CMOS PLA's
Julio Ortega, A. Prieto, A. Lloris, Francisco J. Pelayo · IEEE Transactions on Circuits and Systems · 1991
The authors present a built-in self-test (BIST) programmable logic array (PLA) design in CMOS technology that provides a high percentage of coverage for multiple stuck-at, crosspoint, and bridging faults and, furthermore detects all simple stuck-open faults in the AND and OR planes and all multiple stuck-open faults in the AND plane. As the test patterns used are the same for all PLAs, a universal test for PLAs is defined. The hardware overhead complexity for this scheme resembles that of previous proposals, although the number of different test patterns used has been reduced.>