Defect-tolerant routing algorithm for low power NoCs based on buffer-shared router architecture
Long Xia, Yuchun Ma, Ning Xu · 2013
Low power consumption and reliability become vital in Network-on-Chip (NoC) designs with growth of integrated circuits complexity. In this paper, we propose a novel architecture with buffer-shared router structure to reduce buffer redundancy. Accordingly, the proposed defect-tolerant routing algorithm can effectively associate with improved intra-router architecture to improve reliability of NoCs and reduce power consumption. Simulation results demonstrate the defect-tolerant routing algorithm based on the buffer-shared router architecture can save about 9.7% and 11.2% power consumption and achieve quite high reliability when compared with NF routing algorithm and DyAD routing algorithm in the presence of permanent defects, respectively.