A novel graceful degradable routing algorithm for 3D on-chip networks
Reza Nakhjavani, Ali Shahabi, Saeed Safari, Zainalabedin Navabi · 2012
The decreasing manufacturing yield of integrated circuits, as a result of rising complexity and decreased feature size, and the emergence of 3D-NoC based design architectures, has necessitated the search for network reconfiguration techniques in order to make faulty networks reusable. In this paper, we first introduce an efficient and scalable hardware based on using a fixed size programmable routing table (PRT) for each network switch. Then a heuristic search algorithm is provided to find a valid configuration for these PRTs and to compensate the effects of faulty links in three dimensional networks on chip. Our experimental results show that the algorithm considerably reduces the required search effort as compared to the exhaustive search method.