Fast VLSI architectures using nonredundant multibit recoding for computing AY mod N
B.S. Prasanna, P. V. Ananda Mohan · IEE Proceedings - Circuits Devices and Systems · 1994
A recently proposed technique for multiplication using two-bit recoding, which does not require subtraction operations, is extended for fast AB mod N evaluation. Architectures considering 2, 4, 8 and 16 bit recoding are considered and compared regarding the ALU complexity and speed requirements.