Error correction circuit using difference-set cyclic code
Yukihiro Kato, Tomokazu Morita · 2003
An error correction receiver using difference-set cyclic code has been designed. Highly reliable operation, short critical path, and small circuit size are key issues. The synchronization circuit is optimized in its circuit size by detecting 10 kinds of bit sequences for synchronization. The circuit action is governed by state machine combined with a Johnson counter and a timer. The critical path length is estimated to be 4.8, which is less than average value.