Sequential circuit test generation by real number simulation
Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi · Systems and Computers in Japan · 1993
Abstract This paper presents a test generation method using an optimization technique for a single stuck‐at fault in synchronous sequential circuits. This method utilizes a new real number simulation for defining the cost of an input pattern for a given fault and leads an input pattern to a test pattern by changing the input repeatedly to minimize its cost. Since a sequential circuit has internal states, a test pattern for a fault is a sequence of input vectors for several time frames. For generating the whole test pattern, the concept of forward test generation, which performs the convergence calculation process at multiple time frames, is introduced to avoid the problem of local optimum. Experimental results for ISCAS '89 benchmark sequential circuits show the effectiveness of the proposed method for sequential circuit test generation.