An analog neurochip and its applications to multilayered artificial neural networks
Daiki Masumoto, Hiroki Ichiki, H. Yoshizawa, Hideki Kato, Kazuo Asakawa · Electronics and Communications in Japan (Part II Electronics) · 1991
Abstract A multipurpose neurochip (analog neuroprocessor) has been developed that incorporates neural networks into equipment. This paper describes this analog neurochip and the multilayered artificial neural networks that run on it. This chip was built using 2‐μm Bi‐CMOS technology. Input/output signals are analog and weights are digital. An analog time‐sharing bus is used for input and output; analog data can be sampled at intervals of 13 μ. An example of the exclusive‐OR problem has been included. Construction of a three‐layered network using the chips required development of a system that consists of the following: chip memory to store weights board on which chips, memories, and control circuit are mounted software simulator dedicated to error backprop‐agation learning This system performs parallel processing in each network layer and executes pipeline processing between the layers. It has a processing speed of up to 0.6 million interconnections per second (MIPS). The current chip has some problems, including dispersion of device characteristics, loss of significant digits of weight, and digit overflow. Some countermeasures for these problems also are examined.