System verification using multilevel concurrent simulation
Karen Panetta Lentz, Jamie Heller, Pier Luca Montessoro · IEEE Micro · 1999
The verification of multilevel designs in a single simulator environment can be achieved efficiently using concurrent simulation. MCS is a research simulation tool developed in conjunction with Compaq Computer Corporation and Draper Laboratories. MCS overcomes limitations imposed by merged simulator approaches. MCS achieves this by incorporating techniques that are not specific to any abstraction level, making it attractive for testing interface interconnects and mixed-mode logic. We describe our approach, which is a cohesive simulator platform based on concurrent simulation algorithms.