A 45nm 37.3GOPS/W heterogeneous multi-core SoC
Yoichi Yuyama, Masayuki Itô, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Makoto Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Richard Kimura, Hironori Kasahara, Hideo Maejima · 2010
A 648 MHz 153.8 mm245 nm CMOS SoC integrates eight general-purpose CPUs, four dynamically reconfigurable processors, two 1024-way matrix-processors, peripherals and interfaces. Using core enhancement, DDR3-I/F improvement and clock buffer deactivation, this SoC achieves 37.3 GOPS/W at 1.15 V.