A message passing coprocessor for distributed memory multicomputers
Jiun-Ming Hsu, Prithviraj Banerjee · Conference on High Performance Computing (Supercomputing) · 1990
The authors present the architecture, methodology and performance evaluation of a message-passing coprocessor (MPC) which can accelerate message communication in a distributed memory multicomputer (i.e. iPSC/2 hypercube). The MPC is a microprogrammable processor which offloads from the CPU the burden of communication and speeds up the software processing by directly executing message passing instructions in microcode. It supports process scheduling, message buffer management, and fast buffer copying. The most unique feature of the MPC is that it performs software caching for expected message destinations and buffers. The MPC works closely with a virtual channel router which is a smart routing controller and supports virtual channels and cached circuits. The software and hardware overhead of communication can be reduced significantly by these two processors. The performance is confirmed by trace-driven simulation. >