ON THE SYNTHESIS OF MASSIVELY PARALLEL ARCHITECTURES
Lothar Thiele, U. Arzt · International Journal of High Speed Electronics and Systems · 1993
We describe synthesis methods for massively parallel architectures. In particular, a methodology is proposed which leads to a mechanical and provably correct design of systems consisting of memory banks, switches, and processor arrays. In particular, the trajectory is based on the concept of piecewise-linear/regular algorithms and processor arrays. Complex design transformations such as partitioning, clustering, control generation, and flattening/creation of hierarchical levels are embedded in a homogeneous design flow. The final specification of the implementation not only contains the processing elements but also control flow, control processors and interfaces to memory banks and switches.