Exploring cross-layer power management for PGAS applications on the SCC platform
Marc Gamell, Iván Rodero, Manish Parashar, Rajeev Muralidhar · 2012
High-performance parallel computing architectures are increasingly based on multi-core processors. While current commercially available processors are at 8 and 16 cores, technological and power constraints are limiting the performance growth of the cores and are resulting in architectures with much higher core counts, such as the experimental many-core Intel Single-chip Cloud Computer (SCC) platform. These trends are presenting new sets of challenges to HPC applications including programming complexity and the need for extreme energy efficiency.