Bit-serial dual basis systolic multipliers for GF(2/sup m/)
S.T.J. Fenn, Mohammed Benaissa, DAVID J. TAYLOR · 2002
A bit-serial dual basis systolic multiplier for GF(2/sup m/) is presented. In addition to carrying out bit-serial, 2-variable input multiplication, the presented multiplier can also carry out constant multiplication and if one of the inputs is entered in bit-parallel form, the hardware requirements of the multiplier can be reduced still further. The proposed multiplier is suitable for use in high speed Reed-Solomon decoders such as in inverse transform circuits and recursive extension circuits. This multiplier is an improved and extended version of a bit-serial systolic multiplier previously presented by the authors.