High-speed fault simulation for UNIVAC 1107 computer system
Irvin H Yetter · 1968
A high-speed logic simulation system of programs with the ability to simulate logic faults has been implemented for the UNIVAC(R) 1107 Computer System. The central simulator program is capable of achieving an average speed of less than one-half microsecond per logical element and has a capacity of up to 10,000 logical components, with a simulated memory of 256 bytes. Among the techniques employed to achieve the speed are (1) logical component “levelizing,” an automatic logic equation ordering method, (2) compiler method of equation evaluation, (3) parallel or simultaneous evaluations of the model, (4) storage of the model equations in main memory storage and (5) for fault simulation, parallel fault perturbations.