Gigabit CDRs Equalizers
John T. Stonick, Jri Lee · 2007
Two critical technologies for the design of robust Gb/s communication links are clock and data recovery (CDR) circuits and equalizers. As communication links operate at higher speeds, the symbol intervals are becoming extremely short. At 40Gb/s the entire bit interval is only 25ps! Two papers in this session provide innovative solutions to the problem of operating CDR circuits in CMOS at such speeds. An additional challenge of realizing CDR circuits in shrinking technologies is coping with performance degradation of analog circuit elements. One paper in this session overcomes this challenge with an all-digital CDR. Of course, for a CDR to operate properly; it often requires an equalizer to improve the input signal quality. However, applications and channel degradation vary widely and thus require a broad range of equalizers optimized differently for complexity and power consumption. In this session, 3 equalizer solutions are presented. Finally, while CDR circuits are critical to the performance of most digital communication systems, the session concludes with an interesting study of the power/performance tradeoffs of utilizing transparent mode repeaters in memory interfaces.