Neural net and Boolean satisfiability models of logic circuits
Srimat Chakradhar, Vishwani D. Agrawal, M.L. Bushnell · IEEE Design & Test of Computers · 1990
Two recently proposed models of digital circuits that are useful in parallel test-generation methods are described. In the neural net model, the input and output signal states of a logic gate are related through an energy function. In the Boolean satisfiability model, a logic gate is represented by a truth expression. How the equivalence of these models offers the flexibility of using the same algorithm in two different environments is shown. The models can be used in parallel methods for solving CAD problems such as simulation and test generation.>