High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA
Tomáš Dědek, Tomáš Martínek, Tomáš Marek · 2007
In this paper, we investigate three different realizations of the same block from different points of view. The mentioned different realizations include two realizations with embedded processors (custom 16-bit RISC processor and general soft-core processor) and the third realization uses Handel-C as an example of synthesisable high-level abstraction languages. The results show that development time of complete solution (HW and SW) is approximately the same for the Handel-C design and the design with soft-core processor; the development time of the Custom 16-bit RISC processor is about five times higher. Moreover, the throughput of the Handel-C design measured in the number of bits processed in one second is the highest. The obtained frequency and occupied area of the Handel-C design depends on the complexity of the used program. However, results are comparable or even better than results of the embedded processors.