Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB
Malay Haldar, Anshuman Nayak, Alok Choudhary, Prith Banerjee · 2000
We p r e s e n t a high-level synthesis framework to synthesize optimized hardware on FPGAs from algorithms described in MATLAB.We focus on a framework to pipeline loops present in the input application.We present a range of scheduling algorithms to obtain the pipeline schedule and discuss their comparative strengths.The synthesized hardwares have been mapped to a Xilinx XC4028 FPGA with external memory and corresponding experimental results are included.Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.To copy