Design of a configurable multichannel interrupt controller
Wei Chipin, Li Zhao lin, Zheng Qingwei, Ye Jianfei, Shenglong Li · 2010
Flexibility of interrupt controller is more and more concerned with the development of System-on-Chip(SoC). In this paper, a configurable multichannel interrupt controller is proposed. Interrupt priority is configurable for processor by accessing registers through ARB bus interface. Combination interrupt is also realized for one Interrupt Service Routing (ISR) to service multiple interrupts at a time. Up to 60 interrupt inputs and 12 interrupt channels are supported in this design. The synthesis time delay in SMIC O.13um CMOS technology is J.43ns.